The invention concerns generally the timing arrangements that determine the relations between the operation of a telecommunication device and a time base of a telecommunication system. Especially the invention concerns such timing arrangements in a situation where a single telecommunication device may operate in at least two telecommunication systems which have separate time bases. Digital cellular radio networks are dealt with as exemplary telecommunication systems.
The concept of a frame period in one form or another constitutes the basis for most timing arrangements in a majority of telecommunication systems, although the definitions for a frame may vary. A frame is generally a piece of information that can be handled separately. A frame period is a time period of constant length and it represents the time which is available for handling a single frame. For example in the known GSM system (Global System for Mobile communications) there have been determined the concepts of a logical frame and a transmission frame: a logical frame is the piece of information that represents a speech period of 20 ms, and a transmission frame is a cyclically repeated time interval of approximately 4.615 ms that determines the radio transmission and reception turns of the base stations and mobile terminals. When synchronization between different telecommunication systems is contemplated, the timing and mutual arrangement of transmission frames is of primary importance.
FIG. 1 illustrates a known arrangement for maintaining transmission frame synchronization in a mobile terminal of a digital cellular radio network. The radio transceiver 101 of the mobile terminal comprises a voltage controlled oscillator or VCO 102 and an automatic frequency control unit or AFC unit 103 for maintaining the oscillation frequency of the VCO exactly at a certain value which is determined by the base station (not shown) with which the mobile terminal is communicating. A derivation block 104 converts the frequency of the VCO into a suitable lower frequency known as the Frame Time Counter input clock or FTC input for short.
The derivation block may be a single functional block or it may consist of distributed frequency division and/or multiplication units. The FTC input frequency is typically very closely related to the symbol or chip frequency: it may be for example four or eight times the symbol or chip frequency. It is conducted to a Frame Time Counter or FTC 105 which is simply a counter the value of which is incremented by one per each period of the FTC input.
The length of a frame period has been stored in a Frame Length Register or FLR 106, and comparison means 107 are arranged as a part of or in close association with the FTC to compare the value of the FTC against the stored frame length in the FLR. Each time the FTC reaches the value that corresponds to the stored frame length, the FTC is reset and the value of a Frame Counter or FC 108 is incremented by one. The purpose of the FC is to keep track of the unique identification number of the current frame. It may contain either the full number of each frame or a shortened number in which latter case it is on the responsibility of other parts of the timing arrangement to map the current shortened value in the FC to a full identification number of the current frame.
An Interrupt Timing Register or ITR 109 is provided for storing the value(s) of the FTC that require interrupts to be generated. There may be also multiple ITRs. Each time the corresponding comparison means 110 detect that the value of the FTC equals a value stored in (one of) the ITR(s) they will generate an interrupt to a processor 111. The operation of the processor is determined by the software 112 which the processor is executing: one of the functions of the software is to detect and identify the interrupts and to take whatever action that has been associated with a certain interrupt. There is also a connection from the processor to the FC 108.
The system of FIG. 1 is only applicable for implementing the frame synchronization of one telecommunication system. Currently the mobile terminals of digital cellular radio networks are evolving towards multimode operation which means that a single terminal should be able to selectably communicate with at least two different telecommunication systems with no common time base. Handovers from one system to another should be as seamless as possible, and while a terminal is communicating with one system it should be able to perform synchronized signal strength measurements and other operations in the other system(s). There exists therefore a need for a frame synchronization system that would simultaneously provide exact synchronization information relating to at least two telecommunication systems.
FIG. 2 illustrates an obvious modification to the system of FIG. 1 to enable double-mode frame synchronization. It has been assumed that a single VCO 102xe2x80x2 in a certain transceiver 101xe2x80x2 is used as the source for the timing signals. There are provided, in parallel, two derivation blocks 104xe2x80x2, two FTCs 105xe2x80x2, two FLRs 106xe2x80x2, two FCs 108xe2x80x2, two ITRs 109xe2x80x2 and two comparison means 107xe2x80x2 and 110xe2x80x2. The processor 111 executes a first software 201 to comply with the requirements of a first telecommunication system and a second software 202 to comply with the requirements of a second telecommunication system. The processor receives interrupts from both frame synchronization circuit arrangements, and xe2x80x9csoftxe2x80x9d comparisons are made between the interrupt moments to determine the mutual relations of the frame timings. The idea can be generalized to multimode terminals by adding parallel synchronization circuit arrangements and interrupt lines to the processor.
The drawback of the system of FIG. 2 is its dependency on software execution and interrupt signals. Even with real time operating systems it is difficult to make a processor react to two different interrupts with exactly the same time constant, whereby error is introduced into the synchronization arrangement. Even if the processor would react promptly to all interrupts there may be different delays outside the processor in the generation of the interrupts, and in a practical case the outside delays will add up with the internal interrupt detection and response uncertainties to produce an unpredictable source of timing errors.
It is an object of the present invention to provide a synchronization method and arrangement for realizing multimode frame synchronization with high accuracy. A further object of the invention is to provide such a synchronization method and arrangement with reasonably low circuit complexity and current consumption. An additional object is to provide the synchronization arrangement in a form that is readily produced in the form of an integrated circuit.
The objects of the invention are achieved by latching a snapshot of the values of certain frame timing counters and frame counters into a register at known time instants.
It is characteristic to the circuit arrangement according to the invention that it comprises
a first counter and a second counter,
first snapshot storage means responsive to a first triggering signal for storing the value of said first counter that coincides with the reception of said first triggering signal and
a processor for reading the stored value of said first counter and for timing an operational step so that its timing in relation to the timing of a first telecommunication system is known.
The invention applies also to a method comprising the characteristic steps of
a) regularly updating a first counter value at a pace determined by the first telecommunication system,
b) regularly updating a second counter value at a pace determined by the second telecommunication system,
c) at a first time instant storing the current first counter value,
d) at a second, later time instant reading the counter value stored at step c) and
e) using the counter value read at step d) to time an operational step so that its timing in relation to the timing of the first telecommunication system is known.
Additionally the invention applies to a radio telecommunication device for communicating with a first telecommunication system and a second telecommunication system. It is characteristic to the radio telecommunication device that it comprises
a first counter responsive to the frame time counter input clock generated in a first radio transceiver,
a second counter responsive to the frame time counter input clock generated in a second radio transceiver,
first snapshot storage means responsive to a first triggering signal for storing the value of said first counter that coincides with the reception of said first triggering signal and
a processor for reading the stored value of said first counter and for timing an operational step so that its timing in relation to the timing of the first telecommunication system is known.
According to the invention there is provided a first frame synchronization arrangement for keeping track of the frame timing of a first telecommunication system, and a second frame synchronization arrangement for keeping track of the frame timing of a second telecommunication system. Snapshot storage means are provided for temporarily storing exact values that describe the state of at least one frame synchronization arrangement at a given time instant. The snapshot storage means are responsive to certain triggering signals so that said given time instants will correspond to the issue of the triggering signals.
Several alternatives are available for the generation of the triggering signals. According to a first alternative there are snapshot storage means for each frame synchronization arrangement and a processor will issue the triggering signals directly so that it will inherently know the time instant which certain existing contents of the snapshot storage means will correspond to. There may even be only one triggering line through which a triggering signal will be conducted simultaneously to all snapshot storage means. In a simplified version of the first alternative there is one frame synchronization arrangement without snapshot storage means and the processor will rely on frame synchronization information from that frame synchronization arrangement in issuing the trigger commands to the existing snapshot storage means.
According to a second alternative a first frame synchronization arrangement will issue a triggering signal to the snapshot storage means of a second frame synchronization arrangement at a time instant the relation of which to the frame timing in the first frame synchronization arrangement is known. Redundancy may be introduced into the second alternative by cross-exchanging the triggering signals so that the first frame synchronization arrangement will trigger the snapshot storage means of a second frame synchronization arrangement and vice versa.
According to a third alternative there is a separate triggering signal generator that will issue triggering signals to all snapshot storage means either simultaneously or according to a known schedule.